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HI-8282A
January 2006
ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER FEATURES
! ARINC specification 429 compliant ! Alternate source to Intersil HS-3282 in all ARINC 429 applications ! Small footprint 44-pin QFP package option ! 16-Bit parallel data bus ! Direct receiver interface to ARINC bus ! Timing control 10 times the data rate ! Selectable data clocks ! Automatic transmitter data timing ! 8 word transmit FIFO ! Receiver error rejection per ARINC specification 429 ! Self test mode ! Parity functions ! Low power, single 5 volt supply ! Industrial & full military temperature ranges
GENERAL DESCRIPTION
The HI-8282A is a silicon gate CMOS device for interfacing the ARINC 429 serial data bus to a 16-bit parallel data bus. Two receivers and an independent transmitter are provided. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The transmitter section provides the ARINC 429 communication protocol. Additional interface circuitry such as the Holt HI-8585, HI-8586 or HI-3182 is required to translate the 5 volt logic outputs to ARINC 429 drive levels. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOS and TTL. Timing of all the circuitry begins with the master clock input, CLK. For ARINC 429 applications, the master clock frequency is 1 MHz. Each independent receiver monitors the data stream with a sampling rate 10 times the data rate. The sampling rate is software selectable at either 1MHz or 125KHz. The results of a parity check are available as the 32nd ARINC bit. The HI-8282A examines the null and data timings and will reject erroneous patterns. For example, with a 125 KHz clock selection, the data frequency must be between 10.4 KHz and 15.6 KHz. The transmitter has a First In, First Out (FIFO) memory to store 8 ARINC words for transmission. The data rate of the transmitter is software selectable by dividing the master clock, CLK, by either 10 or 80. The master clock is used to set the timing of the ARINC transmission within the required resolution.
PIN CONFIGURATION (Top View)
- N/C - 429DI2(B) - 429DI2(A) - 429DI1(B) - 429DI1(A) - VCC - N/C - MR - TXCLK - CLK - N/C
N/C - 1 D/R1 - 2 D/R2 - 3 SEL - 4 EN1 - 5 EN2 - 6 BD15 - 7 BD14 - 8 BD13 - 9 BD12 - 10 BD11 - 11
44 43 42 41 40 39 38 37 36 35 34
APPLICATIONS
! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion
HI-8282APQI HI-8282APQT HI-8282APQM
33 - N/C 32 - N/C 31 - CWSTRX 30 - ENTX 29 - 429DO 28 - 429DO 27 - TX/R 26 - PL2 25 - PL1 24 - BD00 23 - BD01
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional Package Pin Configurations)
(DS8282A Rev. E)
HOLT INTEGRATED CIRCUITS www.holtic.com
N/C - 12 BD10 - 13 BD09 - 14 BD08 - 15 BD07 - 16 BD06 - 17 GND - 18 BD05 - 19 BD04 - 20 BD03 - 21 BD02 - 22
01/06
HI-8282A
PIN DESCRIPTION
SYMBOL
VCC 429DI1 (A) 429DI1 (B) 429DI2 (A) 429DI2 (B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 PL1 PL2 TX/R 429DO 429DO ENTX CWSTR CLK TX CLK MR
FUNCTION
POWER INPUT INPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POWER I/O I/O I/O I/O I/O I/O INPUT INPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT OUTPUT INPUT +5V 5%
DESCRIPTION
ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag Receiver 2 data ready flag Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if EN1 is high Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus 0V Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. "ONES" data output from transmitter. "ZEROES" data output from transmitter. Enable Transmission Clock for control word register Master Clock input Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. Master Reset, active low
HOLT INTEGRATED CIRCUITS 2
HI-8282A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8282A contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each flip flop provides options to the user as follows:
DATA BUS
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with the receiver or the transmitter. ARINC bit 1 is the first bit transmitted or received. BYTE 1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
DATA BUS PIN
BDO5
FUNCTION CONTROL
DESCRIPTION
If enabled, an internal connection is made passing 429DO and 429DO to the receiver logic inputs If enabled, ARINC bits 9 and, 10 must match the next two control word bits If Receiver 1 Decoder is enabled, the ARINC bit 9 must match this bit If Receiver 1 Decoder is enabled, the ARINC bit 10 must match this bit If enabled, ARINC bits 9 and 10 must match the next two control word bits If Receiver 2 Decoder is enabled, then ARINC bit 9 must match this bit If Receiver 2 Decoder is enabled, then ARINC bit 10 must match this bit Logic 0 enables normal odd parity and Logic 1 enables even parity output in transmitter 32nd bit CLK is divided either by 10 or 80 to obtain XMTR data clock CLK is divided either by 10 or 80 to obtain RCVR data clock
ARINC BIT
SELF TEST
0 = ENABLE
BYTE 2
DATA BUS ARINC BIT BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO6
RECEIVER 1 DECODER
1 = ENABLE
BDO7
-
-
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels:
BDO8
-
-
BDO9
RECEIVER 2 DECODER
1 = ENABLE
BD10
-
-
STATE ONE NULL ZERO
DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts
BD11
-
-
The HI-8282A guarantees recognition of these levels with a common mode Voltage with respect to GND less than 5V for the worst case condition (4.75V supply and 13v signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data.
BD12
INVERT XMTR PARITY XMTR DATA CLK SELECT RCVR DTA CLK SELECT
1 = ENABLE
BD13
0 = /10 1 = /80 0 = /10 1 = /80
HI-8282A-10
The HI-8282A-10 option is similar to the HI-8282A with the exception that it allows an external 10 Kohm resistor to be added in series with each ARINC input without affecting the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required. Each side of the ARINC bus must be connected through a 10 Kohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 10 Kohm resistors, they are just below the standard 6.5 V minimum ARINC data threshold and just above the 2.5 V maximum ARINC null threshold. The receivers of the HI-8282A-10 when used with external 10 Kohm resistors will withstand DO-160D, Level 3, waveforms 3, 4 and 5A. No additional lightning protection circuit is necessary. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt Line Drivers and Receivers.
BD14
vcc
429DI1(A) OR 429DI2(A)
GND
DIFFERENTIAL AMPLIFIERS
COMPARATORS
ONES
NULL
vcc
429DI1(B) OR 429DI2(B)
ZEROES
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS 3
HI-8282A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION Figure 2 shows a block diagram of the logic section of each receiver. BIT TIMING The ARINC 429 specification contains the following timing specification for the received data: HIGH SPEED LOW SPEED 100K BPS 1% 12K -14.5K BPS BIT RATE 10 5 sec PULSE RISE TIME 1.5 0.5 sec 10 5 sec PULSE FALL TIME 1.5 0.5 sec 5 sec 5% 34.5 to 41.7 sec PULSE WIDTH The HI-8282A accepts signals that meet these specifications and rejects outside the tolerances. The way the logic operation achieves this is described below: 1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be considered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed.
3. Each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. In this manner the bit rate is checked. With exactly 1MHz input clock frequency, the acceptable data bit rates are as follows: HIGH SPEED DATA BIT RATE MIN DATA BIT RATE MAX 83K BPS 125K BPS LOW SPEED 10.4K BPS 15.6K BPS
4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is incremented. A count of 3 will enable the next reception. RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit, ARINC bit 32. If the result is odd, then "0" will appear in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). If the receiver decoder is enabled and the 9th and 10th ARINC bits match the control word program bits or if the receiver decoder is disabled, then EOS clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The data flag for a receiver will remain low until after both ARINC bytes from that receiver are retrieved. This is accomplished by activating EN with SEL, the byte selector, low to retrieve the first byte and activating EN with SEL high to retrieve the second byte. EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2. If another ARINC word is received and a new EOS occurs before the two bytes are retrieved, the data is overwritten by the new word.
TO PINS SEL EN D/R DECODER CONTROL BITS
MUX CONTROL
32 TO 16 DRIVER
CONTROL BIT BD14
CLOCK OPTION
CLOCK
CLK
/
LATCH ENABLE CONTROL BITS 9 & 10
32 BIT LATCH BIT COUNTER AND END OF SEQUENCE
32 BIT SHIFT REGISTER
DATA
PARITY CHECK
32ND BIT
BIT CLOCK
EOS
EOS
ONES
WORD GAP
WORD GAP TIMER
BIT CLOCK
SHIFT REGISTER
START
END
NULL
SHIFT REGISTER
SEQUENCE CONTROL
ZEROS
SHIFT REGISTER
ERROR
ERROR DETECTION
CLOCK
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS 4
HI-8282A
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO are internally connected to the receivers inputs, bypassing the interface circuitry. Data to Receiver 1 is as transmitted and data to Recevier 2 is the complement. 429DO and 429DO outputs remain active during self test.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1 and then PL2 to load byte 2. The control logic automatically loads the 31 bit word in the next available position of the FIFO. If TX/R, the transmitter ready flag, is high (FIFO empty), then 8 words, each 31 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 8 positions are full, the FIFO ignores further attempts to load data.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data may be overwritten if not retrieved within one ARINC word cycle. 2. The FIFO can store 8 words maximum and ignores attempts to load addition data if full. 3. Byte 1 of the transmitter data must be loaded first. 4. Either byte of the received data may be retrieved first. Both bytes must be retrieved to clear the data ready flag. 5. After ENTX, transmission enable, goes high it cannot go low until TX/R, transmitter ready flag, goes high. Otherwise, one ARINC word is lost during transmission.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at either 429DO or 429DO. The 31 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks
ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME
The word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, TX/R, high.
MASTER RESET (MR)
On a Master Reset data transmission and reception are immediately terminated, the transmit FIFO and receivers cleared as are the transmit and receive flags. The Control Register is not affected by a Master Reset.
BIT BD12 DATA AND NULL TIMER SEQUENCER
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
31 BIT PARALLEL LOAD SHIFT REGISTER
BIT CLOCK
PARITY GENERATOR
429DO 429DO
WORD CLOCK
BIT AND WORD GAP COUNTER
START SEQUENCE
8 X 31 FIFO
ADDRESS
LOAD
WORD COUNTER AND FIFO CONTROL
INCREMENT WORD COUNT
TX/R ENTX
DATA BUS
DATA CLOCK
FIFO LOADING SEQUENCER
PL1 PL2
DATA CLOCK DIVIDER
CLK TX CLK
FIGURE 3.
TRANSMITTER BLOCK DIAGRAM
CONTROL BIT BD13
HOLT INTEGRATED CIRCUITS 5
HI-8282A
FUNCTIONAL DESCRIPTION (cont.)
REPEATER OPERATION
The repeater mode of operation allows a data word that has been received by the HI-8282A to be placed directly into its FIFO for transmission. After a 32-bit word has been shifted into the receiver shift register, the D/R flag will go low. A logic "0" is placed on the SEL line and EN is strobed. This is the same procedure as for normal receiver operation and it places the lower byte (16) of the data word on the data bus. By strobing PL1 at the same time as EN,
the byte will also be placed into the transmitter FIFO. SEL is then taken high and EN is strobed again to place the upper byte of the data word on the data bus. By strobing PL2 at the same time as EN, the second byte will also be placed into the FIFO. The data word is now ready to be transmitted according to the parity programmed into the control word register. In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into the FIFO and the transmitter FIFO is always loaded with the lower byte of the data word first.
TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN
429DO
ARINC BIT
429DO
DATA NULL DATA NULL DATA NULL
BIT 30
BIT 31
BIT 32
WORD GAP
BIT 1 NEXT WORD
LOADING CONTROL WORD
DATA BUS
VALID
tCWSET tCWHLD
CWSTR
tCWSTR
RECEIVER OPERATON
ARINC DATA
BIT 31 BIT 32
DATA READY FLAG
D/R
tD/R
BYTE SELECT SEL
DON'T CARE DON'T CARE
tEND/R tEN tSELEN tENEN tDATAEN
BYTE 1 VALID BYTE 2 VALID
DON'T CARE
tSELEN
ENABLE BYTE ON BUS EN
tENSEL
tENSEL
tD/REN
DATA BUS
tDATAEN
tENDATA
tENDATA
HOLT INTEGRATED CIRCUITS 6
HI-8282A
TIMING DIAGRAMS (cont.)
TRANSMITTER OPERATION
DATA BUS BYTE 1 VALID BYTE 2 VALID
tDWSET
PL1
tDWHLD
tDWSET
tDWHLD tPL12
tPL
PL2
tPL12
TX/R
tPL
tTX/R
TRANSMITTING DATA
PL2
tDTX/R tPL2EN
TX/R
ENTX
tENDAT
429DO or 429DO
ARINC BIT
tENTX/R
DATA BIT 2 DATA BIT 32
DATA BIT 1
REPEATER OPERATION TIMING
429DI BIT 32
tEND/R
D/R
tD/R
EN
tD/REN
tEN
tENEN
tEN
tSELEN
SEL
DON'T CARE
tENSEL
DON'T CARE
tENPL
PL1
tPLEN tENPL
tSELEN
tENSEL tPLEN
PL2
tTX/R
TX/R
tTX/REN
ENTX
tENTX/R
tENDAT
429DO BIT 1
tDTX/R
BIT 32
tNULL
HOLT INTEGRATED CIRCUITS 7
HI-8282A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vcc Voltage at ARINC Inputs Voltage at any other pin DC Current Drain per input pin -0.3V to +7V -29V to +29V -0.3V to Vcc +0.3V 10mA Power Dissipation Operating Temperature Range: (Industrial) (Military) Storage Temperature Range: 500mW -40C to +85C -55C to +125C -65C to +150C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V 5%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITIONS
MIN
LIMITS
TYP MAX
UNIT
ARINC INPUTS
-
429DI1 (A), 429DI1 (B), 429DI2 (A) & 429DI2 (B) ONE ZERO NULL Differential To GND To Vcc Input Sink Input Source Differential To GND To Vcc VIH VIL VNUL RI RG RH IIH IIL CI CG CH Pins 2 to 3, 4 to 5 ARINC Input Pins: Common mode voltage less than 5V with respect to GND 6.5 -13.0 -2.5 12 12 12 10.0 -10.0 0 13.0 -6.5 2.5 V V V KW KW KW 200 -450 20 20 20 A A pF pF pF
Differential Input Voltage:
Input Resistance:
27 27
Input Current: Input Capacitance: (Guaranteed but not tested)
BI-DIRECTIONAL INPUTS - BD00 through BD15 Input Voltage: Input Current: Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 2.1 0.7 1.5 -1.5 V V A A
ALL OTHER INPUTS - SEL, EN1, EN2, PL1, PL2, ENTX, CWSTR, CLK & MR Input Voltage: Input Current: Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 3.5 0.7 10 -20 V V A A
OUTPUTS - D/R1, D/R2, BD00 through BD15, TX/R, 429DO, 429DO & TX CLK Output Voltage: Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: SUPPLY INPUT - VCC Standby Supply Current: Operating Supply Current: ICC1 ICC2 20 20 mA mA Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source Output Sink Output Source VOH VOL IOL IOH IOL IOH CO IOH = -1.5mA IOL = 2.6mA VOUT = 0.4V VOUT = VCC - 0.4V VOUT = 0.4V VOUT = VCC - 0.4V 2.7 0.4 3.0 1.1 2.6 1.1 15 V V mA mA mA mA pF
HOLT INTEGRATED CIRCUITS 8
HI-8282A
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
CONTROL WORD TIMING Pulse Width - CWSTR Setup - DATA BUS Valid to CWSTR HIGH Hold - CWSTR HIGH to DATA BUS Hi-Z RECEIVER TIMING Delay - Start ARINC 32nd Bit to D/R LOW: High Speed Low Speed Delay - D/R LOW to EN L0W Delay - EN LOW to D/R HIGH Setup - SEL to EN L0W Hold - SEL to EN HIGH Delay - EN L0W to DATA BUS Valid Delay - EN HIGH to DATA BUS Hi-Z Pulse Width - EN1 or EN2 Spacing - EN HIGH to next EN L0W FIFO TIMING Pulse Width - PL1 or PL2 Setup - DATA BUS Valid to PL HIGH Hold - PL HIGH to DATA BUS Hi-Z Spacing - PL1 or PL2 Delay - PL2 HIGH to TX/R LOW TRANSMISSION TIMING Spacing - PL2 HIGH to ENTX HIGH Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - EN LOW to PL LOW Hold - PL HIGH to EN HIGH Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing tENPL tPLEN tTX/REN tMR 0 0 0 200 1% ns ns ns ns tPL2EN tENDAT tENDAT tDTX/R tENTX/R 0 0 25 200 400 s s s ns ns tPL tDWSET tDWHLD tPL12 tTX/R 200 110 10 0 840 ns ns ns ns ns tD/R tD/R tD/REN tEND/R tSELEN tENSEL tENDATA tDATAEN tEN tENEN 200 50 0 200 20 20 200 30 16 128 s s ns ns ns ns ns ns ns ns tCWSTR tCWSET tCWHLD 130 130 0 ns ns ns
SYMBOL
LIMITS MIN TYP MAX
UNITS
HOLT INTEGRATED CIRCUITS 9
HI-8282A
ADDITIONAL HI-8282A PIN CONFIGURATIONS
(See page 1 for the 44-pin Plastic Quad Flat Pack )
44-PIN PLASTIC PLCC
44-PIN J-LEAD CERQUAD
HI-8282APJI HI-8282APJT HI-8282APJM
HI-8282ACJI HI-8282ACJT HI-8282ACJM
44-PIN CERAMIC LCC
40-PIN CERAMIC SIDE BRAZED DIP
Vcc (REC. 1 INPUT) 429DI1(A) (REC.1 INPUT) 429DI1(B) (REC. 2 INPUT) 429DI2(A) (REC. 2 INPUT) 429DI2(B) (REC.1 DATA FLAG) D/R1 (REC.2 DATA FLAG) D/R2 (REC. BYTE SELECT) SEL (REC. 1 OUTPUT ENABLE) EN1 (REC. 2 OUTPUT ENABLE) EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
NC MR CLK NC NC CWSTR (CONTROL WORD STROBE) ENTX (ENABLE XMIT) 429DO (XMIT DATA) 429DO (XMIT DATA) TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND (XMIT READY FLAG) (XMIT BYTE 2 LE) (XMIT BYTE 1 LE) (MASTER RESET) (MASTER CLK IN) TX CLK (XMIT CLOCK OUT)
HI-8282ACLI HI-8282CLT HI-8282CLM
HI-8282ACDI / CDT / CDM
HOLT INTEGRATED CIRCUITS 10
HI-8282A
ORDERING INFORMATION
HI - 8282A Cx x -xx (Ceramic)
PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY
No dash number -10 (Note 1)
PART NUMBER
35 Kohm 25 Kohm
FLOW
0 10 Kohm
BURN IN LEAD FINISH
TEMPERATURE RANGE
I T M
PART NUMBER
-40C TO +85C -55C TO +125C -55C TO +125C
PACKAGE DESCRIPTION
I T M
NO NO YES
Gold Gold Tin / Lead (Sn / Pb) Solder
CD CJ CL
40 PIN CERAMIC SIDE BRAZED DIP 44 PIN J-LEAD CERQUAD 44 PIN CERAMIC LEADLESS CHIP CARRIER
HI - 8282A Px x x -xx (Plastic)
PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY
No dash number -10 (Note 1)
PART NUMBER LEAD FINISH
35 Kohm 25 Kohm
0 10 Kohm
Blank F
PART NUMBER
Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE RANGE FLOW BURN IN
I T M
PART NUMBER
-40C TO +85C -55C TO +125C -55C TO +125C
PACKAGE DESCRIPTION
I T M
NO NO YES
PJ PQ
NOTES:
44 PIN PLASTIC J-LEAD PLCC (Note 2) 44 PIN PLASTIC QUAD FLAT PACK (Note 2)
1. The -10 configuration requires an external 10Kohm resistor in series with each ARINC input to guarantee specified voltage thresholds. 2. Both the 44-pin J-lead PLCC package and the 44-pin PQFP package are rated as Moisture Sensitivity Level (MSL) 1 and do not require special moisture handling precautions.
HOLT INTEGRATED CIRCUITS 11
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
40-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 40C
2.020 MAX (51.308 MAX)
.610 .010 (15.494 .254)
.595 .010 (15.113 .254)
.225 MAX (5.715 MAX)
.050 TYP (1.270 TYP)
.085 .009 (2.159 .229)
.600 .010 (15.240 .254)
.125 MIN (3.175 MIN)
.018 TYP (.457 TYP)
.100 BSC (2.540 BSC)
.010 +.002/.001 (.254 +.051/.025)
44-PIN J-LEAD CERQUAD
Package Type: 44U
2 1 44 43
.688 .005 (17.475 .127) MAX. SQ.
.620 .012 (15.748 .305)
.650 .010 (16.510 .254) SQ. .039 .005 (.990 .127) .019 .002 (.483 .051) .050 TYP. (1.270) .200 (5.080)MAX. .100 .007 (2.540 .178)
HOLT INTEGRATED CIRCUITS 12
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type: 44J
PIN NO. 1 .045 x 45 PIN NO. 1 IDENT .045 x 45 .050 .005 (1.27 .127) .690 .005 (17.526 .127) SQ. .653 .004 (16.586 .102) SQ. .031 .005 (.787 .127) .017 .004 (.432 .102)
SEE DETAIL A .172 .008 (4.369 .203) .610 .020 (15.494 .508)
.009 .011
.015 .002 (.381 .051) .020 MIN (.508 MIN) R .025 .045
DETAIL A
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type: 44PQS
.007 MAX. (.17)
.547 .010 (13.90 .25) SQ.
.394 .004 (10.0 .10) SQ.
.0315 BSC (.80 BSC) .014 ..002 (.35 .05) .035 +.006 / -.004 (.88 +.15 / -.10)
See Detail A
.097 MAX. (2.45) .079 +.004 / -.006 (2.00 +.10 / -.15) .008 TYP. (.20 R)
.012 TYP. (.30 R)
0 Q 7
Detail A
HOLT INTEGRATED CIRCUITS 13
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
44-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 44S
.020 INDEX (.508 INDEX) PIN 1
.040 x 45 3 PLCS (1.016 x 45 3 PLCS) .050 .005 (1.270 .127)
.075 .004 (1.905 .101)
.326 .006 (8.280 .152)
PIN 1
.651 .011 (16.535 .279) SQ.
.050 BSC (1.270 BSC) .009R .006 (.229R .152)
.025 .003 (.635 .076) .092 .028 (2.336 .711)
HOLT INTEGRATED CIRCUITS 14

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